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Components and Subsystems

TheCPUincludesasingledigitalthermalsensor(DTS)thatcontinuouslymeasuresthe

temperatureateachprocessingcoreandprovidesprocessordietemperatureinformation

thatrepresentstheworstcasetemperatureforallcores.TheDTSdatarepresentsthe

differencebetweenthecurrentdietemperatureandthetemperatureatwhichtheATM

activatesthethermalcontrolcircuitry.TheIPMCaccessesDTSinformationthroughthe

platformenvironmentalcontrolinterface(PECI).

Formoreinformationonthetemperaturesensors,refertoManagedsensorsonpage 104.

Integrated memory controller

TheintegratedCPUmemorycontrollersupportsuptothreeindependentchannelsof

DDR3DIMMs,using64databitsand8ECCbitsperchannel.Whenrunningat800MHz,

theCPMsupportsupto64GBofDDR3memory.At1066 MHz,itsupportsupto48GB.

RefertoDDR3SDRAMon

page 34formoreinformationabouttheDIMMsandto

SupportedDIMMcombinationsonpage 17formoreinformationaboutCPMDIMM

configurations.

Memory modes

Thememorycontrolleroperatesinindependentmode.Independentmodeallowsthe

memorycontrollertointerleavethememorymapacrossallthreechannels,resultingin

thehighestlevelofperformance.Inindependentmode,DIMMscanbeplacedinanyof

thethreechannelsandtherearenomatchingrequirementsforrankorDIMMspeed.A

burst‐lengthof8isused.

Note:

•MaximumperformanceisachievedonlywhentheDIMMsareidenticallypopulated

acrossthethreechannels.

•TheCPMonlysupportsregisteredECCDDR3DIMMs;itdoesnotsupportunbuffered

DIMMs(withorwithoutECC).

DRAM temperature control

TheCPUcaninfluencetheDRAMtemperaturebyreducingthememorychannel

frequency(throttling).TheCPMtriggersafrequencydecreasebyassertinga

DDR_THERM#inputtotheCPUwhenevertheDIMMtemperaturegetstoohigh

(implementedbywiringtogethertheEVENT#pinsfromeachDIMM).

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RadiSys ATCA-5400 RTM Specifiche Pagina 32